The final part of the specification of a memory upgrade is the speed of the devices needed. As already describe in the previous chapter, access speed is measured in nano-seconds or ns. The slowest devices have access times of 150ns to 120ns. Medium speed devices are 100ns and fast access chips are 80ns, 65ns and 60ns. In most cases it isn’t possible to look at the design of a machine and easily deduce the speed of RAM chips needed. Indeed some systems will allow you to use one of a number of speed by imposing additional wait states for slower chips. If machine uses page mode memory access then it may even be more stringent in the type of chips it uses than simply specifying an overall access speed.
The simplest solution to finding out what type of chips your machine needs it to look in the manual! Failing this you cloud open the case and look for the area where the existing memory is installed and read the device code on one of the chips – see Reading the chips. You can usually recognize where the memory device are either because they will be the only SIP/SIMM device or because they will be arranged in a regular rectangular array of identical DIL chips.
It doesn’t really matter if you use chips that are faster than your machine needs. They won’t male it work any faster and they will cost more but at least they will work. This is one solution if you simply cannot find out what speed of memory device to use. On the order hand, Using chips that are slower than your machine needs will cause memory errors to be reported during the power on Self Test (POST) routine . It is even possible that if the chips are only a little slower than your machine needs then they will pass the POST routine but fail intermittently later on when your machine has warmed up a little. (RAM chips are more tolerant of being worked faster when they are cooler.)
Most machines have to be informed , either via jumpers, dip switches or software setup, if what speed chips you are using so that they can the appropriate number of wait states. Once again introducing more wait states than necessary will
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